In general, gate capacitance means a capacitance applied between channel area and gate of FET(field effect transistor). Referring to FIG. 1, a typical gate capacitance characteristic of FET is depicted. As can be seen in FIG. 1, the gate capacitance has a value of C0 above threshold voltage(Vt), and at a range of below Vp(.apprxeq.Vt), it has a remained parasitic capacitance(C1) of about 1/10 of C0 value, which is caused by the rapid reduction of the capacitance while free carrier disappeared at the channel area.
The effects of the gate capacitance characteristics on a circuit is described in more detail with references on the accompanying drawings, which show a circuit of a high frequency power amplifier employing FET (see: FIG. 2) and a pattern of signal waveform distortion at the gate terminal of the power amplifier(see: FIG. 3).
The circuit depicted in FIG. 2 may be operated in a class of B, AB or F, where gate bias voltage is set around Vp as shown in FIG. 1. Referring to FIG. 2, the sine wave signal(Vin) is inputted to an input matching part of the power amplifier, while a distorted waveform such as Vg(t) occurs at the gate terminal of FET. This distorted waveform is shown more specifically in FIG. 3, where the gate signal waveform Vg(t) is a combined one of the gate bias voltage (Vp) and the gate input signal.
Referring to FIG. 3, time course of the gate signal waveform Vg(t) is shown, where Vg(t) rapidly changes to a spike at a voltage range(2) lower than Vp, while it changes slowly at a voltage range(1) higher than Vp. If the Vp biased sine wave are applied to the gate terminal (G) without any distortion, the voltage above Vp will be applied to the gate terminal for a period equivalent to 180.degree. within one cycle of the sine wave. However, the waveform distortion shown in FIG. 3 does not coincide with the expectation, where the voltage above Vp is applied to the gate terminal longer than the expectation. This phenomenon is caused by the change of capacitance of the impedance of the gate terminal depending on the voltage(see: FIG. 1), while the impedance of the input matching part, due to the linearity, remains constant regardless of the magnitude of the signal(see: FIG. 2).
The degree of waveform distortion is directly related with the ratio of C0 and C1(see: FIG. 1): The larger the ratio is, the severer the distortion becomes, and a non-distorted waveform which is close to the sine wave is provided, when the ratio is near 1. In addition, when the sine wave without any distortion is inputted to the gate of FET, FET is turned on for a period equivalent to 180.degree. of one cycle. However, since the distorted waveform is actually applied to the gate as shown in FIG. 3, FET is turned on more longer than the period equivalent to 180.degree..
Due to the reason illustrated as aboves, the drain(D) current becomes overflowed, which results in the drop of the overall efficiency of the amplifier(see: Paul M. White, IEEE MTTs, pp.277-230(1994); Masahiro Maeda, IEEE MTTs, pp.579-582(1995); Kyeik Jeon, IEEE MTTs, pp.817-820(1997)).
According to the simulation studies, the amplifier whose gate is operated in a distorted waveform as in FIG. 3, requires more D.C. electric power more than that operated by the sine wave by the percentage of 30%, which means the reduction of the efficiency of about 30%. Therefore, the reduction of the efficiency can be prevented by controlling or avoiding the waveform distortion. And, the distortion can be properly controlled by regulating the ratio, since the distortion depends on the nonlinearity of the gate capacitance, i.e., the ratio of the capacitances at the range of below and above Vp.
The nonlinearity of capacitance may affect on the linearity of the power amplifier, in addition to the reduction of efficiency. At the gate, the voltage swing is larger at the lower input voltage than that of at the higher input voltage. Moreover, since the capacitance is nonlinear, the impedance of gate may be varied depending on the inputted voltage, which causes the occurrence of so-called "phase distortion", by which the phase of output according to the input of the amplifier changes depending on the electric power. Therefore, if the capacitance of gate remains constant without the dependence of the gate voltage, the gate impedance will have a constant value regardless of the applied voltage, which results in the reduction of the phase distortion.
In this connection, a method for controlling the distortion of the sine wave by regulating the ratio of the gate capacitance in a range of above and below Vp viewed from the X side of FIG. 2 to have a value of approximately 1, has been suggested in the art. This method was realized by employing a shunt capacitor(Cs) between the gate terminal and source terminal of FET as in FIG. 4(A) (see: Paul M. White, IEEE MTTs, pp.277-280(1994)). This circuit, as can be seen in FIG. 4(B), has its merits of relaxing the nonlinearity of the gate capacitance by increasing the capacitance at the input terminal of FET to the level of Cs. However, the prior art circuit is proven to be less satisfactory in the sense that matching of impedance of the amplifier input terminal is very difficult, due to the increase of admittance of the input terminal of the FET by the increased amount of the gate capacitance.
Under the circumstance, a method which employs a circuit supplemented with a LC series circuit between source terminal and gate terminal of FET has been suggested. This circuit, grounded on a fact that the waveform distortion shown in FIG. 3 is resulted from the second high frequency which is caused mainly by the nonlinearity of the gate capacitance, controls the waveforms distortion by locating a LC series circuit which has a characteristic of resonating at the second harmonic frequency, between the source terminal and the gate terminal and then by controlling the component of the second harmonic frequency. However, this method also have revealed shortcomings such that: it can be applied only in the circuit with narrow frequency band, because the inductance and capacitance should be changed according to the signal frequency applied to FET.
Accordingly, there are strong reasons for exploring and developing alternative means for controlling waveform distortion at a gate terminal of FET, while overcoming the problem that their operating frequency are rather limited and matching of the input impedance is difficult, due to the use of linear device such as capacitor.